1. Field of the Invention
The invention relates to a device to check the end of a test aimed at achieving reliability in manufacturing tests performed on memories of all types.
2. Discussion of the Related Art
With the currently used submicron semiconductor technologies, it is important to carry out thorough tests on all the integrated circuits that come off the production line. For memories in integrated circuit form (or integrated circuits comprising memories) it is possible to test all the memory cells one by one by reading and then writing in each of the cells of this memory successively and repetitively. However, the ever greater sizes of memories are making these tests increasingly time consuming. To speed up the testing at the manufacturer's premises, accelerated testing procedures have been devised. In a memory organized in rows and columns, it is possible, for example, to load the data into one or more columns simultaneously on all the rows. Several test vectors may be sent in this way throughout the memory at far greater speed than by normal access. Besides, certain large-capacity memories can have one or more rows and or columns of additional memory cells used to replace defective cells if any. The test procedure will be used to connect the additional cells where they are needed.
Certain memories have read-protected and/or write-protected access zones that are not accessible (or accessible only once) in normal memory operation, and need to be tested. Those skilled in the art often resort to a mode of testing that permits certain operations specific to the manufacturer's testing stage. Since the running of the testing stages is not the object of the present patent application, those skilled in the art may refer to the many publications pertaining to accelerated tests, test vectors, memory repairing by cell substitution or the like, irrespective of whether they are serial-access or parallel-access memories of the SRAM, DRAM, ROM, PROM, EPROM or EEPROM type with or without protected access zones. The invention relates more particularly to the locking of the test phase.
U.S. Pat. No. 5,264,742 (hereinafter called the '742 patent), refers to the problem of locking the test phase of a chip card memory (with protected access zone). In the '742 patent, it is explained that the test phase needs to be locked because otherwise it is possible to access the protected access zone during the test phase. The locking is strictly prohibited in normal use. The '742 patent therefore uses two locks: one is conditioned by the other while the other can be activated only once. Although a reading of the '742 patent suggests that the test mode needs to be permanently locked for security reasons, there is no explanation given of how to ascertain that the locking is working properly, since the lock may be defective.
Furthermore, there are other types of memory for which the locking of the test mode is particularly worthwhile. In serial-access memories for example, the various operations possible (reading, writing, launching of tests, erasure, etc.) may be activated by instructions sent to an input/output pin that corresponds to the data and/or address input/output. There is a risk that an operating error might activate the launching of the test if it is not locked, thus possibly destroying the data elements present in the memory.
In the case of parallel-access memories, it is possible to have additional pins that are used solely for the test and must be neutralized (for example grounded) during normal operation. It is also possible that, in test mode, certain pins will be used for functions different from normal operation. In order to avoid operating errors, it is preferable to lock the manufacturing test. Naturally, for all the types of memory, it is possible to have available a test at the disposal of the user in normal operation of the integrated circuit. The user's test will be far more limited than the manufacturer's test and will not be capable of destroying data or enabling access to read-protected and/or write-protected zones.